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intel strataflash wireless memory system (lv18/lv30 scsp) 768-mbit lvq family with asynchronous static ram datasheet product features the intel strataflash ? wireless memory system (lv18/lv30 scsp); 768-mbit lvq family with asynchronous static ram device offers a high performance code and large embedded data segment plus ram combination in a common package with electrical quad+ ballout on 0.13 m etox? viii flash technology. the code segment flash die features 1.8 v low-power operations with flexible, multi-partition, dual operation read-while-write / read-while-erase, asynchronous and synchronous burst reads at 54 mhz. the data segment flash die features 1.8 v low-power operations optimized for cost sensitive asynchronous data applications. this device integrates up to three flash dies, two psram dies, and one sram die in a low-profile package compatible with other scsp families using the quad+ ballout package. device architecture code and data segment: 128- and 256- mbit density; psram: 32- and 64-mbit density; sram: 8 mbit density. top or bottom parameter configuration. asymmetrical blocking structure. 16-kword parameter blocks (top or bottom); 64-k word main blocks. zero-latency block locking. absolute write protection with block lock down using f-wp#. device voltage core: v cc = 1.8 v (typ). i/o: v ccq = 1.8 v or 3.0 v (typ). device concurrent operations (3 dies) buffered efp: 600 kb per second. erase performance: 384 kb per second (main blocks). device packaging 88 balls (8 x 10 active ball matrix). area:8x10mmor8x11mm. height: 1.0 mm to 1.4 mm. quality and reliability extended temp: C 25 cto+85 c. minimum 100 k flash block erase cycle. xram performance psram at 1.8 v i/o : 85 ns initial access, 30 ns async page reads; 65 ns initial access, 18 ns async page. sram at 1.8 or 3.0 v i/o: 70 ns initial access. flash performance code segment at 1.8 v i/o: 85 ns initial access; 25 ns async page read; 14 ns sync reads (t chqv ); 54 mhz clk. data segment at 1.8 v i/o: 170 ns initial access; 55 ns async page read. flash architecture hardware read-while-write/erase. 8-mbit or 16-mbit multi-partition. 2-kbit one-time programmable (otp) protection register. software read-while-write/erase. single full-die partition size. flash software intel fdi, intel psm, and intel vfm. common flash interface (cfi). basic/extended command set. 253852-002 december 2003 notice: this document contains information on new pr oducts in production. the specifications are subject to change without notice. verify with your local intel sales office that you have the lat- est datasheet before finalizing a design.
2 datasheet informationinthisdocumentisprovidedinconnectionwithintel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the lv18/lv30 scsp datasheet may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtained by calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com. *other names and brands may be claimed as the property of others. copyright ? intel corporation, 2003
datasheet 3 contents contents 1.0 introduction ............................................................................................................................... .....5 1.1 nomenclature ................................................................................................................ .......5 1.2 acronyms .................................................................................................................... ..........7 1.3 conventions................................................................................................................. .........7 2.0 functional overview .....................................................................................................................9 2.1 device description........................................................................................................... .....9 3.0 package information ...................................................................................................................11 3.1 one- and two-die scsp....................................................................................................11 3.2 four-die scsp ................................................................................................................ ...12 3.3 one-die intel ut-scsp ...................................................................................................13 3.4 two-die intel ut-scsp ...................................................................................................14 3.5 three-die intel ut-scsp ................................................................................................15 4.0 ballout and signal descriptions ................................................................................................16 4.1 signal descriptions .......................................................................................................... ...18 5.0 maximum ratings and operating conditions ...........................................................................21 5.1 absolute maximum ratings ................................................................................................21 5.2 operating conditions ......................................................................................................... .22 6.0 electrical specifications .............................................................................................................23 6.1 dc current characteristics .................................................................................................23 7.0 ac characteristics ......................................................................................................................25 7.1 scsp device ac test conditions ......................................................................................25 7.2 sram and psram capacitance........................................................................................25 7.3 sram ac read specifications...........................................................................................25 7.4 sram ac write specifications ...........................................................................................27 7.5 psram ac read specifications ........................................................................................30 7.6 psram ac write specifications ........................................................................................32 8.0 power and reset specifications ................................................................................................34 9.0 design guide: operation overview ...........................................................................................35 9.1 bus operations ............................................................................................................... ....35 9.2 flash device commands and command definitions .........................................................36
contents 4 datasheet 10.0 flash read operation ................................................................................................................. 37 11.0 flash program operation ........................................................................................................... 37 12.0 flash erase operation ................................................................................................................ 37 13.0 flash suspend and resume operations ................................................................................... 37 14.0 flash block locking and unlocking operations ...................................................................... 37 15.0 flash protection register operation ......................................................................................... 37 16.0 flash configuration operation ................................................................................................... 37 17.0 dual operation considerations .................................................................................................. 38 17.1 product configurations and memory partitioning ............................................................... 38 17.2 product segment unique features .................................................................................... 39 17.3 flash die memory map....................................................................................................... 40 18.0 psram operations ...................................................................................................................... 45 18.1 psram power-up sequence and initialization................................................................... 45 18.2 psram mode register....................................................................................................... 45 18.2.1 psram mode register setting ............................................................................. 46 18.2.2 cautions for setting psram mode register ......................................................... 47 18.3 psram low-power mode .................................................................................................. 48 appendix a write state machine ........................................................................................................ 49 appendix b common flash interface ................................................................................................. 49 appendix c flash flowcharts ............................................................................................................. 49 appendix d additional information .................................................................................................... 50 appendix e ordering information ....................................................................................................... 51 revision history date revision description 10/03r -001 initial release 12/03 -002 in the valid combinations table: added line item mehcanical and ordering information for 256l+256v+64p+64p. deleted the tbd 5-die stack option. revised the matrix table.
768-mbit lvq family with asynchronous static ram datasheet 5 1.0 introduction this document provides information about the intel strataflash ? wireless memory system (lv18/ lv30 scsp); 768-mbit lvq family with asynchronous static ram device, including information on the features, characteristics, operations, and specifications for: ? code and data segment flash dies ? sram and psram dies the intent of this document is to provide information where this 768-mbit lvq family with asynchronous static ram stacked chip scale package (scsp) device differs from the intel strataflash ? wireless memory system (lv18/lv30 scsp); 1024-mbit lv family device. refer to the latest revision of the intel strataflash ? wireless memory system (lv18/lv30 scsp; 1024- mbit lv family datasheet (order number 253854) for flash product details not included in this document. 1.1 nomenclature 0x hexadecimal prefix 0b binary prefix byte 8 bits cfi common flash interface du dont use etox eprom tunnel oxide k (noun) 1 thousand kb 1024 bits kb 1024 bytes kword 1024 words m (noun) 1 million mb 1,048,576 bits mb 1,048,576 bytes otp one-time programmable rcr read configuration register rfu reserved for future use scsp stacked chip scale package sr status register srd status register data word 16 bits 1.8 v core range of 1.7 v C 1.95 v 1.8 v i/o range of 1.7 v C 1.95 v asserted signal with logical voltage level v il , or enabled deasserted signal with logical voltage level v ih , or disabled high-z tri-stated or high impedance low-z driven
768-mbit lvq family with asynchronous static ram 6 datasheet non-array reads flash reads which return flash device identifier, cfi query, protection register and status register information program an operation to write data to the flash array write bus cycle operation at the inputs of the flash die, in which a command or data are sent to the flash array block group of cells, bits, bytes or words within the flash memory array that get erased with one erase instruction parameter block any 16-kword flash array block. main block any 64-kword flash array block. top parameter previously referred to as a top-boot device, a device with flash parameter partition located at the highest physical address of its memory map for processor system boot up. bottom parameter previously referred to as a bottom-boot device, a device with flash parameter partition located at the lowest physical address of its memory map for processor system boot up. bottom-top parameter stacked-csp device configuration of two flash dies in the same segment arranged with the parameter partitions located at the lowest and highest physical address of its memory map. partition a group of flash blocks that shares common status register read state. parameter partition a flash partition containing parameter and main blocks. main partition a flash partition containing only main blocks. die individual physical flash die used in a stacked-csp memory subsystem device segment a section of the scsp memory subsystem divided for different operating characteristics. the scsp memory subsystem has three segments: a code segment, a data segment, and an xram segment. code segment a segment that contains one or two flash memory dies optimized for fast code or data reads. each die features multi-partition synchronous read-while-write or burst read-while-erase capability. data segment a segment contains one or two flash memory dies optimized for large embedded data. each die feature single-partition asynchronous read, write, and erase operations. xram segment a segment contains one or two xram memory dies. the xram combinations could include sram, psram, or lpsdram. subsystem a stacked memory integration concept made up of multiple memory dies arranged in code, data, and xram segments. device an individual flash die or a flash + xram scsp.
768-mbit lvq family with asynchronous static ram datasheet 7 1.2 acronyms buffered-efp buffered enhanced factory programming cui command user interface otp one-time programmable plr protection lock register pr protection register rcr read configuration register rfu reserved for future use (all unused active signals in a package ballout) sr status register wsm write state machine aps automatic power savings cfi common flash interface mlc technology multi-level-cell technology rwe read-while-erase rww read-while-write 1.3 conventions vcc signal or voltage connection v cc signal or voltage level set logical one (1) clear logical zero (0) 0x hexadecimal number prefix 0b binary number prefix sr[4] denotes an individual flash status register bit, in this case bit 5 of sr[7:0]. d[15:0] denotes a group of similarly named signals, such as data bus. a5 denotes one element of a signal group membership, in this case address bit 5. f[3:1]-ce#, f[2:1]-oe# this is the method used to refer to more than one chip-enable or output enable at the same time. when each is referred to individually, the reference will be f1-ce# and f1-oe# (for die #1), f2-ce# and f2-oe# (for die #2), and f3-ce# and f3-oe#(for die #3). f denotes the flash specific signal and ce# is the root signal name of the flash die. other
768-mbit lvq family with asynchronous static ram 8 datasheet notation includes: s to denote sram, p to denote psram, d to denote lpsdram, and r to denote common ram type signal names. adv# denotes a global signal of the device, address valid because there is no die specific reference.
768-mbit lvq family with asynchronous static ram datasheet 9 2.0 functional overview this section provides an overview of the code and embedded data segment features and capabilities of the 768-mbit lvq family with asynchronous static ram device. 2.1 device description the 768-mbit lvq family with asynchronous static ram device incorporates flash dies used as code segment flash memory and large embedded data segment flash memory, along with xram for a high performance, cost-effective high density memory system solution. this stacked device uses the latest intel strataflash ? wireless memory system on 0.13 m etox? viii process technology. the code segment is a high performance, multi-partition, synchronous burst-mode read-while- write (rww) or read-while-erase (rwe) flash memory die, while the large, embedded data segment is a cost efficient, single-partition, asynchronous flash memory die. the package for this device is available in a quad+ ballout, which supports flash only or flash + psram and/or sram stacked memory combinations. the scsp in a quad+ ballout with a 0.8 mm ball pitch, 8x10 active ball matrix supports a memory subsystem up to 66 mhz on a x16-bit bus width. see figure 1, lv18/lv30 device family block diagram on page 9 for device block diagram. figure 1. lv18/lv30 device family block diagram lvq family f-wp# code segment optional flash die # 3 (128- or 256-mbit) flashdie#1 (128- or 256-mbit) data segment optionalflashdie#3 (128- or 256-mbit) flashdie#2 (128- or 256-mbit) f1-ce# f2-ce# f3-ce# f3-ce# f-rst# f[2:1]-oe# f-we# wait adv# clk a[max:min] d[15:0] s-cs2 r-we# r-oe# p-mode / p-cre p[2:1]-cs# s-cs1# r-lb# p-vcc s-vcc r-ub# vss xram segment die # 2 64-or128-mbit psram die # 1 32- 64- or 128- mbit psram die#3 8-mbit sram f-vpp f-vcc vccq
768-mbit lvq family with asynchronous static ram 10 datasheet the 768-mbit lvq family with asynchronous static ram device consists of a 1.8 v flash memory device with 1.8 v and 3.0 v i/o options. as shown in figure 1, lv18/lv30 device family block diagram on page 9 , the device is available with a minimum of one flash die each per code segment and data segment (flash die # 1 and flash die #2). an optional third flash die is available for either the code or data segment. see table 1, 768 mbit lvq family matrix on page 10 for possible combinations. designed for low-voltage systems, the lvq supports read operations with f-v cc at1.8v,and erase and program operations with f-vpp at 1.8 v. buffered enhanced factory programming (buffered-efp) provides the fastest flash array programming performance, with elevated f-v pp at 9.0 v to increase factory throughput. with f-v pp at 1.8 v, f-vcc and f-vcc can be tied together for a simple, ultra-low-power design. in addition to voltage flexibility, a dedicated f-v pp connection provides complete data protection when f-vpp v pplk . the intel strataflash ? wireless memory system provides data security through its individual zero- latency block lock capability. each memory block can be unlocked, locked, or locked-down by hardware or software control. individualized f-ce# control allows the user to manage which flash die is asserted, furthering the flexibility of power management while controlling data integrity per segment with f-wp#. the f[2:1]-oe# in lvq products with quad+ ballout are common internally table 1. 768 mbit lvq family matrix line item flash components ram components package size notes 1.8 v i/o 256l18 + 256l18 none 8x11x1.2 1 256l18 + 256v18 64ps + 64ps 11x13x1.4 1 3.0 v i/o 256l30 + 256v30 none 8x11x1.2 1 notes: 1. available in top or bottom configurations.
768-mbit lvq family with asynchronous static ram datasheet 11 3.0 package information the 768-mbit lvq family with asynchronous static ram device is available with various die combinations in both the standard stacked chip scale package (scsp) and the intel ? ultra-thin stacked chip scale package (intel ? ut-scsp). 3.1 one- and two-die scsp figure 2. mechanical specifications for one/two-die scsp (8x10 mm) millimeters inches di me n s i on s s ymbol mi n n om max not e s mi n n om max pa ckage height a 1.200 0.0472 ball height a1 0.200 0.0079 pa ckage body thickne s s a2 0.860 0.03 39 ball (lead) width b 0.325 0.375 0.425 0.0128 0.0148 0.0167 pa ckage body length d 9.900 10.000 10.100 0.3898 0.3937 0.3976 pa ckage body width e 7.900 8.000 8.100 0.3110 0.3150 0.3189 pitch e 0.800 0.0315 ball (lead) count n 88 88 se ating plane coplanarity y 0.100 0.0039 corne r t o ball a1 dis tance along e s1 1.100 1.200 1.300 0.0433 0.0472 0.0512 corne r t o ball a1 dis tance along d s2 0.500 0.600 0.700 0.0197 0.0236 0.0276 top view - ball down bottom view - ball up a a2 d e y a1 draw ing not to scale. s2 s1 a c b e d g f j h k l m e 1 2 3 4 5 6 7 8 b a c b e d g f j h k l m a1 index mark 12 345 678 8x10x1.2q
768-mbit lvq family with asynchronous static ram 12 datasheet 3.2 four-die scsp figure 3. mechanical specifications for four-die scsp (11x13 mm) millimeters inches dimens ions symbol min nom max notes min nom max package height a 1.400 0.0551 ball height a1 0.200 0.0079 package body thicknes s a2 1.070 0.0421 ball (lead) width b 0.325 0.375 0.425 0.0128 0.0148 0.0167 package body length d 12.900 13.000 13.100 0.5079 0.5118 0.5157 package body width e 10.900 11.000 11.100 0.4291 0.4331 0.4370 pitch e 0.800 0.0315 ball (lead) count n 88 88 seating plane coplanarity y 0.100 0.0039 corner to ball a1 dis tance along e s1 2.600 2.700 2.800 0.1024 0.1063 0.1102 corner to ball a1 dis tance along d s2 2.000 2.100 2.200 0.0787 0.0827 0.0866 top view - ball down bottom view - ball up a a2 d e y a1 drawing not to scale. s2 s1 a c b e d g f j h k l m e 1 2 3 4 5 6 7 8 b a c b e d g f j h k l m a1 index mark 12345678
768-mbit lvq family with asynchronous static ram datasheet 13 3.3 one-die intel ut-scsp figure 4. mechanical specifications for one-die intel ? ut-scsp (8x11 mm) millimeters inches dimens ions symbol min nom max notes min nom max package height a 1.00 0.0394 ball height a1 0.117 0.0046 package body thicknes s a2 0.740 0.0291 ball (lead) width b 0.300 0.350 0.400 0.0118 0.0138 0.0157 package body length d 10.900 11.00 11.100 0.4291 0.4331 0.4370 package body w idth e 7.900 8.00 8.100 0.3110 0.3150 0.3189 pitch e 0.80 0.0315 ball (lead) count n 88 88 seating plane coplanarity y 0.100 0.0039 corner to ball a 1 distance a long e s1 1.100 1.200 1.300 0.0433 0.0472 0.0512 corner to ball a 1 distance a long d s2 1.000 1.100 1.200 0.0394 0.0433 0.0472 top view - ball down bottom view - ball up a a2 d e y a1 drawing not to scale. s2 s1 a c b e d g f j h k l m e 1 2 3 4 5 6 7 8 b a c b e d g f j h k l m a1 index mark 123 456 78 note: dimensions a1, a2, and b are preliminary
768-mbit lvq family with asynchronous static ram 14 datasheet 3.4 two-die intel ut-scsp figure 5. mechanical specifications for two-die intel ? ut-scsp (8x11 mm) millimeters inches di mensions s ymbol mi n nom max notes min nom max pa ckag e heig h t a 1.200 0.0472 ball height a1 0.200 0.0079 package body thickness a2 0.860 0.0339 ball (lead) width b 0.325 0.375 0.425 0.0128 0.0148 0.0167 pa ckag e bo d y len g th d 10.900 11.000 11.1 00 0.4291 0.43 31 0.4370 pa ckage body w idth e 7.900 8.000 8.100 0.3110 0.3150 0.3189 pitch e 0.800 0.0315 ball (lead) count n 88 88 se ating plane coplanarity y 0.100 0.0039 co rne r t o ball a1 dis tan ce alo n g e s1 1.100 1.200 1.300 0.0433 0.04 72 0.0512 co rne r t o ball a1 dis tan ce alo n g d s2 1.000 1.100 1.200 0.0394 0.04 33 0.0472 top view - ball down bottom view - ball up a a2 d e y a1 draw ing not to scale. s2 s1 a c b e d g f j h k l m e 1 2 3 4 5 6 7 8 b a c b e d g f j h k l m a1 index mark 12 3456 78
768-mbit lvq family with asynchronous static ram datasheet 15 3.5 three-die intel ut-scsp figure 6. mechanical specifications for three-die intel ? ut-scsp (8x11 mm) millimeters inches di me ns i ons s ymbol mi n nom max not e s mi n nom max package height a 1.20 0.0472 ball height a1 0.117 0.0046 package body thicknes s a2 0.910 0.0358 ball (lead) w idth b 0.300 0.350 0.400 0.0118 0.0138 0.0157 package body length d 10.900 11.00 11.100 0.4291 0.4331 0.4370 package body w idth e 7.900 8.00 8.100 0.3110 0.3150 0.3189 pitch e 0.80 0.0315 ball (lead) count n 88 88 seating plane coplanarity y 0.100 0.0039 corner to ball a1 dis tance along e s1 1.100 1.200 1.300 0.0433 0.0472 0.0512 corner to ball a1 dis tance along d s2 1.000 1.100 1.200 0.0394 0.0433 0.0472 top view - ball down bottom view - ball up a a2 d e y a1 draw ing not to scale. s2 s1 a c b e d g f j h k l m e 1 2 3 4 5 6 7 8 b a c b e d g f j h k l m a1 index mark 1 234 567 8 note:dimensionsa1, a2,andbarepreliminary
768-mbit lvq family with asynchronous static ram 16 datasheet 4.0 ballout and signal descriptions figure 7, quad+ signal ballout for lvq device family shows the signal ballout for the 768- mbit lvq family with asynchronous static ram device, ideal for space-constrained board applications and allowing density upgrades without pcb redesign. the user is responsible to adapt for density upgrade flexibility in the pcb design.
768-mbit lvq family with asynchronous static ram datasheet 17 figure 7. quad+ signal ballout for lvq device family flash specific sram/psram specific global legend: top view - ball side down 8 7 6 5 4 3 2 1 a b c d e f g h j k l m du a4 du du du du du du du a5 a3 a2 a7 a1 a6 a0 a18 a19 vss vss a23 a24 a25 a17 f2-vcc clk a21 a22 a12 a11 a13 a9 p1-cs# f-vpp, f-vpen a20 a10 a15 f-we# a8 d8 d2 d10 d5 d13 wai t a14 a16 f1-ce# p-mode, p-cre vss vss vss p2-cs# f1-vcc f2-vcc vccq f3-ce# d0 d1 d9 d3 d4 d6 d7 d15 d11 d12 d14 f1-oe# f2-oe# p-vcc s-cs2 r-we# r-ub# r-lb# r-oe# s-vcc s-cs1# f1-vcc f-wp# adv# f-rst# f2-ce# vccq vss vss vccq vss
768-mbit lvq family with asynchronous static ram 18 datasheet 4.1 signal descriptions table 2 describes the active signals used on the 768-mbit lvq family with asynchronous static ram device. table 2. signal descriptions (sheet 1 of 3) symbol type description a[max:min] input address inputs: inputs for all die addresses during read and write operations. ? 256-mbit die : amax= a23 ? 128-mbit die : amax = a22 ? 64-mbit die : amax = a21 ? 32-mbit die : amax = a20 ? 8-mbit die : amax = a18 a0 is the lowest-order 16-bit wide address. a[25:24] denote high-order addresses reserved for future device densities. d[15:0] input/ output data inputs/outputs: inputs data and commands during write cycles, outputs data during read cycles. data signals float when the device or its outputs are deselected. data are internally latched during writes on the flash device. f[3:1]-ce# input flash chip enable: low-true input. f[3:1]-ce# low selects the associated flash memory die. when asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. when deasserted, the associated flash die is deselected, power is reduced to standby levels, data and wait outputs are placed in high-z state. f1-ce# selects or deselects flash die #1; f2-ce# selects or deselects flash die #2 and is rfu on combinations with only one flash die. f3-ce# selects or deselects flash die #3 and is rfu on stacked combinations with only one or two flash dies. s-cs1# s-cs2 input sram chip select: low-true / high-true input (s-cs1# / s-cs2 respectively). when either/both sram chip select signals are asserted, sram internal control logic, input buffers, decoders, and sense amplifiers are active. when either/both sram chip select signals are deasserted, the sram is deselected and its power is reduced to standby levels. s-cs1# and s-cs2 are available on stacked combinations with sram die and are rfu on stacked combinations without sram die. p[2:1]-cs# input psram chip select: low-true input. when asserted, psram internal control logic, input buffers, decoders, and sense amplifiers are active. when deasserted, the psram is deselected and its power is reduced to standby levels. p1-cs# selects psram die #1 and is available only on stacked combinations with psram die. this ball is an rfu on stacked combinations without psram. p2-cs# selects psram die #2 and is available only on stacked combinations with two psram dies. this ball is an rfu on stacked combinations without psram or with a single psram. f[2:1]-oe# input flash output enable: low-true input. f[2:1]-oe# low enables the flash output buffers. f[2:1]-oe# high disables the flash output buffers, and places the selected flash outputs in high-z. f1-oe# controls the outputs of flash die #1; f2-oe# controls the outputs of flash die #2 and flash die #3. f2-oe# is available on stacked combinations with two or three flash die and is rfu on stacked combinations with only one flash die.
768-mbit lvq family with asynchronous static ram datasheet 19 r-oe# input ram output enable: low-true input. r-oe# low enables the selected ram output buffers. r-oe# high disables the ram output buffers, and places the selected ram outputs in high-z. r-oe# is available on stacked combinations with psram or sram die, and is an rfu on flash-only stacked combinations. f-we# input flash write enable: low-true input. f-we# controls writes to the selected flash die. address and data are latched on the rising edge of f-we#. r-we# input ram write enable: low-true input. r-we#controlswritestotheselectedramdie. r-we# is available on stacked combinations with psram or sram die and is an rfu on flash-only stacked combinations. clk input clock: synchronizes the flash die with the system bus clock in synchronous read mode and increments the internal address generator. during synchronous read operations, addresses are latched on the rising edge of adv#, or on the next valid clk edge with adv# low, whichever occurs first. in asynchronous mode, addresses are latched on the rising edge adv#, or are continuously flow-through when adv# is kept asserted. wait output wait: output signal. indicates data is valid in synchronous array or non-array sync flash reads. configuration register bit 10 (cr.10, wt) determines its polarity when asserted. with f-ce# and f-oe# at v il ,waitsactiveoutputisv ol or v oh .waitishigh-zif f-ce# or f-oe# is v ih . ? in synchronous array or non-array flash read modes, wait indicates invalid data when asserted and valid data when deasserted. ? in asynchronous flash page read, and all flash write modes, wait is deasserted. f-wp# input flash write protect: low-true input. f-wp# enables/disables the lock-down protection mechanism of the selected flash die. ? f-wp# low enables the lock-down mechanism where locked down blocks cannot be unlocked with software commands. ? f-wp# high disables the lock-down mechanism, allowing locked down blocks to be unlocked with software commands. adv# input address valid: low-true input. during synchronous flash read operations, addresses are latched on the rising edge of adv#, or on the next valid clk edge with adv# low, whichever occurs first. in asynchronous flash read operations, addresses are latched on the rising edge of adv#, or are continuously flow-through when adv# is kept asserted. r-ub# r-lb# input ram upper / lower byte enables: low-true input. during ram read and write cycles, r-ub# low enables the ram high order bytes on d[15:8], and r-lb# low enables the ram low-order bytes on d[7:0]. r-ub# and r-lb# are available on stacked combinations with psram or sram die and are rfu on flash-only stacked combinations. f-rst# input flash reset: low-true input. f-rst# low initializes flash internal circuitry and disables flash operations. f-rst# high enables flash operation. exit from reset places the flash in asynchronous read array mode. table 2. signal descriptions (sheet 2 of 3)
768-mbit lvq family with asynchronous static ram 20 datasheet p-mode, p-cre input p-mode (psram mode): low-true input. p-mode is used to program the configuration register, and enter/exit low-power mode of psram die. p-mode is available on stacked combinations with asynchronous-only psram die. p-cre (psram configuration register enable): high-true input. p-cre is high, write operations load the refresh control register or bus control register. p-cre is applicable only on combinations with synchronous psram die. p-mode, p-cre s rfu on stacked combinations without psram die. f-vpp, f-vpen power flash program and erase power: valid f-v pp voltageonthisballenables flash program/erase operations. flash memory array contents cannot be altered when f-v pp (f-v pen ) 768-mbit lvq family with asynchronous static ram datasheet 21 5.0 maximum ratings and operating conditions 5.1 absolute maximum ratings warning: stressing the device beyond the absolute maximum ratings may cause permanent damage. these are stress ratings only. operation beyond the operating conditions is not recommended and extended exposure beyond the operating conditions may affect device reliability. notice: this document contains information available at the time of its release. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design . table 3. absolute maximum ratings parameter min max unit notes temperature under bias expanded C25 +85 c 5 storage temperature C55 +125 c 5 voltage on any signal (except f-v cc ,v ccq, f-v pp, s-v cc ,andp-v cc) C0.5 +3.6 v 1,5 f-v cc voltage C0.2 +2.50 v 1,5 v ccq ,p-v cc and s-v cc voltage 1.8v i/o C0.2 +2.50 v 1,5 3.0 v i/o C0.2 +3.60 v 1,5 f-v pp voltage C0.2 +10.0 v 1,2,3,5 i sh output short circuit current C 100 ma 4,5 notes: 1. all specified voltages are relative to v ss . minimum dc voltage is C0.5 v on input/output signals, C0.2 v on v ccq and f-v pp signals. during transitions, this level may overshoot to C2.0 v for periods < 20 ns. maximum dc voltage on f-v cc is v cc + 0.5 v, which during transitions may overshoot to f-vcc +2.0 v for periods <20 ns. maximum dc voltage on input/output signals and vccq is v ccq +0.5 v, which during transitions may overshoot to v ccq + 2.0v for periods < 20ns. 2. maximum dc voltage on f-v pp may overshoot to +10.0 v for periods < 20 ns. 3. flash program/erase voltage (f-v pp ) is typically 1.7 v-2.0 v. f-vpp can be connected to 8.50 v - 9.50 v for 1000 cycles on main blocks and 2500 cycles on parameter blocks, or for 80 hours maximum total. operation with 9.0 v program/erase voltage may reduce flash block cycling capability. 4. output shorted for no more than one second. no more than one output shorted at a time. 5. absolute dc specifications applies to each flash and ram die in the scsp device.
768-mbit lvq family with asynchronous static ram 22 datasheet 5.2 operating conditions table 4. extended temperature operation symbol parameter flash + flash flash + psram flash + psram + sram 2 unit min max min max min max t c operating temperature C25 +85 C25 +85 C25 +85 c f-v cc flash supply voltage 1.7 2.0 1.7 2.0 1.7 2.0 v v ccq p-v cc s-v cc flash i/o voltage psram and sram supply voltage 3.0 v i/o 2.2 3.3 2.7 3.1 2.7 3.1 v 1.8 v i/o 1.7 2.0 1.8 1.95 C C v v ppl 1 f-v pp voltage supply (logic level) 0.9 2 0.9 2 0.9 2 v v pph 1 factory word programming f-v pp 8.5 9.5 8.5 9.5 8.5 9.5 v notes: 1. flash program/erase voltage (f-v pp ) is typically 1.7 v-2.0 v. f-vpp can be connected to 8.50 v - 9.50 v for 1000 cycles on main blocks and 2500 cycles on parameter blocks, or for 80 hours maximum total. operation with 9.0 v program/erase voltage may reduce flash block cycling capability. 2. sram is available only in 3.0 v i/o option.
768-mbit lvq family with asynchronous static ram datasheet 23 6.0 electrical specifications 6.1 dc current characteristics the dc current characteristics referenced in this document are for individual flash and ram die in the scsp device. the total device current is determined by sum of the active and inactive currents of each flash and ram die in the scsp device. note: refer to the latest revision of the intel strataflash ? wireless memory system (lv18/lv30 scsp; 1024-mbit lv family datasheet (order number 253854) for flash dc characteristics not included in this document. sram dc characteristics are shown in table 5 . psram dc characteristics are shown in table 6 on page 24 . notice: individual dc characteristics of all dies in a scsp device need to be considered accordingly, depending on the scsp device stacked combinations and operations. table 5. sram dc characteristics parameter description test conditions 3.0 v sram unit min max s-v cc voltage range C 2.7 3.3 v v dr s-v cc for data retention C 1.5 C v i cc operating current at minimum cycle time i io =0ma C 50 ma i cc2 operating current at maximum cycle time (1 s) i io =0ma C 10 ma i sb standby current s-cs1# s-v cc -0.2v or s-cs2 v ss +0.2v address/data toggling at minimum cycle time C25 a i dr current in data retention mode s-v cc =1.5v C 12 a v oh output high voltage i oh =-100 a s-v cc - 0.1 Cv v ol output low voltage i ol =100 a, v ccmin -0.1 0.1 v v ih input high voltage C s-v cc - 0.4 s-v cc + 0.2 v v il input low voltage C -0.2 0.6 v *i il input leakage current -0.2 < v in 768-mbit lvq family with asynchronous static ram 24 datasheet table 6. psram dc characteristics parameter description test conditions p-v cc = 1.8 v to 1.95 v p-v cc = 2.7 v to 3.1 v unit min typ max min typ max i cc operating current at minimum cycle time i out =0ma CC35 CC45ma i sb1 standby current p-cs# p-v cc - 0.2v,p-mode p-v cc -0.2v 32-mbit C 90 100 C 90 100 a 64-mbit n/a C 110 150 a i sb2 partial array refresh current (standby mode 2) p-cs# p-v cc - 0.2v, p-mode 0.2v 32- mbit 16-mbit C 60 70 C 60 70 a 8-mbit C 50 60 C 50 60 a 4-mbit C 40 50 C 40 50 a 0-mbit C 20 30 C 20 30 a 64- mbit 16-mbit n/a C90110 a 8-mbit C 80 100 a 4-mbit C 70 90 a 0-mbit C 60 80 a i sbd deep power down p-cs# p-v cc - 0.2v, p-mode 0.2v 32-mbit C 20 30 C 20 30 a 64-mbit n/a C 60 80 a v oh output high voltage i oh =-0.5ma 0.8v ccq C C 0.8v ccq CCv v ol output low voltage i ol = 1 ma C C 0.2v ccq C C 0.2v ccq v v ih input high voltage C0.8v ccq C v ccq +0.3 0.8v ccq C v ccq + 0.3 v v il input low voltage C -0.3 C 0.2v ccq -0.3 C 0.2v ccq v *i il input leakage current v in =0vtov ccq C1.0 C +1.0 C1.0 C +1.0 a *i ol input/output leakage current v i/o =0vtov ccq , p-cs# = v ih or r-we# = v ih or r-oe# = v ih C1.0 C +1.0 C1.0 C +1.0 a note: *v in : input voltage, v i/o : input/output voltage.
768-mbit lvq family with asynchronous static ram datasheet 25 7.0 ac characteristics 7.1 scsp device ac test conditions notes: 1. test configuration component value for worst case speed conditions. 2. c l includes jig capacitance. 7.2 sram and psram capacitance sram and psram capacitance is shown in table 7, sram and psram capacitance on page 25 . note: refer to the latest revision of the intel strataflash ? wireless memory system (lv18/lv30 scsp; 1024-mbit lv family datasheet (order number 253854) for flash capacitance details not included in this document. 7.3 sram ac read specifications note: refer to the latest revision of the intel strataflash ? wireless memory system (lv18/lv30 scsp; 1024-mbit lv family datasheet (order number 253854) for flash details not included in this document. figure 8. transient equivalent testing load circuit 1,2 i/o output z o =50ohms c l = 30pf 50 ohms p_v cc /2 = v ccq /2 table 7. sram and psram capacitance symbol parameter max (sram) max (psram) unit condition c in input capacitance 6 8 pf v in =0v c out output capacitance 7 10 pf v out =0v note: sampled, not 100% tested. t c =+25c,f=1mhz.
768-mbit lvq family with asynchronous static ram 26 datasheet table 8. sram ac read specifications # symbol parameter min max unit notes r1 t rc read cycle time 70 C ns r2 t aa address to output delay C 70 ns r3 t co1 s-cs1# to output delay C 70 ns r3 t co2 s-cs2 to output delay C 70 ns r4 t oe r-oe# to output delay C 35 ns r5 t ba r-ub#, r-lb# to output delay C 70 ns r6 t lz s-cs1# or s-cs2 to output in low-z 5 C ns 1,2 r7 t olz r-oe# to output in low-z 0 C ns 1 r8 t hz s-cs1# or s-cs2 to output in high-z 0 25 ns 1,2,3 r9 t ohz r-oe#tooutputinhigh-z 0 25 ns 1,3 r10 t oh output hold (from address, s-cs1#, s-cs2, or r-oe# change, whichever occurs first) 0Cns r11 t blz r-ub#, r-lb# to output in low-z 0 C ns 1 r12 t bhz r-ub#, r-lb# to output in high-z 0 25 ns 1 notes: 1. sampled, not 100% tested. 2. at any given temperature and voltage condition, t hz (max)islessthant lz (max) for a given device and from device-to-device interconnection. 3. timings of t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
768-mbit lvq family with asynchronous static ram datasheet 27 7.4 sram ac write specifications figure 9. sram read waveform table 9. sram ac write specifications (sheet 1 of 2) # symbol parameter min max unit notes w1 t wc writecycletime 70 C ns 1 w2 t as address setup to r-we# (s-cs1#) and r- ub#,r-lb# going low 0Cns3 w3 t wp r-we# (s-cs1#) pulse width 55 C ns 1 w4 t dw data to write time overlap 30 C ns w5 t aw address setup to r-we# (s-cs1#) going high 60Cns w6 t cw s-cs1# (r-we#) setup to r-we# (s-cs1#) going high 60Cns2 w7 t dh data hold from r-we# (s-cs1#) high 0 C ns high z valid output address stable data valid device address selection standby v ih v il v ih v il s-cs1# v ih v il v oh v ol v ih r- o e # r-w e # data r - ub#, r-lb# high z v ih v il r1 r2 r4 r3 r6 r7 r8 r9 r10 s-cs2 v ih v il v ih r5 r11 r12
768-mbit lvq family with asynchronous static ram 28 datasheet w8 t wr write recovery 0 C ns 4 w9 t bw r-ub#, r-lb# setup to r-we# (s-cs1#) going high 60 C ns notes: 1. a write occurs during the s-cs1# and r-we# asserted overlap (t wp ). the write begins with the latest transition of s-cs1# and r-we# going low (r-ub# and/or r-lb# already asserted). the write ends at the earliest transition of s-cs1# or r-we# going high. 2. t cw is measured from s-cs1# going low to the end of a write. 3. t as is measured from address valid to the beginning of a write. 4. t wr is measured from the end of a write to the address change; t wr applied in case a write ends as s- cs1# or r-we# going high. table 9. sram ac write specifications (sheet 2 of 2) figure 10. sram write waveform high z data in address stable device address selection standby addresses v ih v il v ih v il s-cs1# v ih v il v oh v ol v ih r-oe# r- we# data r- ub# , r- lb# high z v ih v il w1 w8 s-cs2 v ih v il v ih w9 w6 w5 w2 w3 w4 w7 table 10. sram data retention timing parameter description min max unit t sdr data retention set-up time 0 C ns t rdr data retention recovery time 70 C ns
768-mbit lvq family with asynchronous static ram datasheet 29 figure 11. sram data retention waveform (s-cs1# controlled) s-v cc s-v ccmin s-v ihmin v dr v ss t sdr data retention mode t rdr s-cs1# figure 12. sram data retention waveform (s-cs2 controlled) s-v cc s -v ccmin v dr v ilmax v ss s-cs2 t sdr data retention mode t rdr
768-mbit lvq family with asynchronous static ram 30 datasheet 7.5 psram ac read specifications table 11. psram ac read specifications # symbol parameter p-v cc = 1.80 v to 1.95 v p-v cc = 2.7 v to 3.1 v unit note min max min max read cycle r1 t rc read cycle time 85 * C65Cns5 r2 t aa address access time C 85 * C65ns5 r3 t co p-cs# low to output valid C 85 * C65ns5 r4 t oe r-oe# low to output valid C 65 C 45 ns r5 t ba r-ub#, r-lb# low to output valid C 85 * C65ns5 r6 t lz p-cs# low to output in low-z 10 C 10 C ns r7 t olz r-oe# low to output in low-z 5 C 5 C ns r8 t hz p-cs# high to output in high-z C 25 C 25 ns r9 t ohz r-oe#hightooutputinhigh-z C 25 C 25 ns r10 t oh output hold from address change 5 C 5 C ns r11 t blz r-ub#, r-lb# low to output in low-z 5 C 5 C ns r12 t bhz r-ub#,r-lb#hightooutputinhigh-z C 25 C 25 ns r13 t aso address set to r-oe# low-level 0 C 0 C ns 1 r14 t ohah r-oe# high-level to address hold -5 C -5 C ns r15 t chah p-cs# high-level to address hold 0 C 0 C ns 1 r16 t bhah r-lb#, r-ub# high-level to address hold 0 C 0 C ns 1,2 r17 t clol p-cs# low-level to r-oe# low-level 0 10,000 0 10,000 ns 3 r18 t olch r-oe# low-level to p-cs# high-level 60 C 45 C ns r19 t cp p-cs# high-level pulse width 10 C 10 C ns r20 t bp r-ub#, r-lb# high-level pulse width 10 C 10 C ns r21 t op r-oe# high-level pulse width C 10,000 C 10,000 ns 3 page mode pr1 t pc page cycle time 30 C 18 C ns 4 pr2 t pa page mode address access time C 30 C 18 ns notes: 1. when r13 | r15|, |r16| and r19 18 ns, the minimum value for r15 and r16 are -15 ns. (see also figure 13, conditions for calculating the minimum value for r15 and r16 on page 31 .) 2. r16 is specified from when both r-lb# and r-ub# become high-level. 3. r17and r21 (max) are applied while p-cs# is being hold at low-level. 4. see figure 14, ac waveform for psram read operations on page 31 . 5. * 32-mbit 1.8v psram initial read access timing specifications changed from 85 ns to 88 ns.
768-mbit lvq family with asynchronous static ram datasheet 31 note: in a read cycle, p-mode and r-we# should be fixed to high-level. figure 13. conditions for calculating the minimum value for r15 and r16 address r-ub#,r-lb#, p-cs# r15, r16 r13 r-oe# figure 14. ac waveform for psram read operations r1 vi h vi l r2 vi h r 3 vi l r8 vi h r 5 vi l r12 vi h r 4 vi l r9 r7 r11 r6 r10 voh high-z high-z vol data out valid output address p-cs# r-ub#, r-lb# r-oe#
768-mbit lvq family with asynchronous static ram 32 datasheet note: in a page read cycle, p-mode and r-we# should be fixed to high-level, and r-ub#, r-lb# are low-level. 7.6 psram ac write specifications figure 15. ac waveform for psram 8-word page read operation table 12. psram ac write specifications # symbol parameter p-v cc = 1.80 v to 1.95 v p-v cc = 2.7 v to 3.1 v unit note min max min max w1 t wc writecycletime 85 C 65 C ns 4 w2 t as address setup time 0 C 0 C ns 1,4 w3 t wp write pulse width 60 C 50 C ns 4 w4 t dw datavalidtowriteend 30 C 35 C ns 4 w5 t aw address valid to end of write 70 C 55 C ns 4 w6 t cw p-cs#toendofwrite 70 C 55 C ns 4 w7 t dh data hold time 0 C 0 C ns 4 w8 t wr write recovery 0 C 0 C ns 4 w9 t bw r-ub#, r-lb# setup to end of write 70 C 55 C ns 4 w10 t cp p-cs# high-level pulse width 10 C 10 C ns 1 w11 t bp r-ub#, r-lb# high-level pulse width 10 C 10 C ns w12 t whp r-we# high-level pulse width 10 C 10 C ns w13 t ohah r-oe# high-level to address hold -5 C -5 C ns w14 t chah p-cs# high-level to address hold 0 C 0 C ns 1 w15 t bhah r-ub#, r-lb# high-level to address hold 0 C 0 C ns 1,2 w16 t oes r-oe# high-level to r-we# set 0 10,000 0 10,000 ns 3 w17 t oeh r-we# high-level to r-oe# set 10 10,000 10 10,000 ns notes: 1. when w2 |w14|, |w15| and w10 18 ns, w14 and w15 (min) are -15 ns. (see also figure 16, conditions for calculating the minimum value for w14 and w15 on page 33 .) 2. w15 is specified from when both r-lb# and r-ub# become high-level. 3.w16andw17(max)areappliedwhilep-cs#isbeingholdatlow-level. 4. see figure 17, ac waveform for psram write operation on page 33 . vih a3-a max valid vil address vih a0,a1,a2 vil 000 r2 pr1 p-cs# r3 pr2 r-oe#, r-ub#, r-lb# r4 r9 voh high- z qn vol data out qn+ 7 qn+ 6 001 111 r1
768-mbit lvq family with asynchronous static ram datasheet 33 notes: 1. during address transition, at least one of the pins p-cs#, r-we#, or both of r-ub# and r-lb# pins should be deasserted. 2. do not input data to the i/o pins while they are in an output state. 3. in a write cycle, p-mode and r-oe# should be fixed to high-level. 4. write operation is done during the overlap time of a low-level p-cs#, r-we#, r-lb# and/or r-ub#. figure 16. conditions for calculating the minimum value for w14 and w15 address r-ub#,r-lb#, p-cs# w14, w15 w2 r-we# w10 figure 17. ac waveform for psram write operation w1 vih vil w2 w8 vih w6 vil w5 vih w9 vil vih w3 vil voh w4 w7 high-z high-z vol address p- cs# r-ub#, r-lb# r-we# data i/o valid data in low-z
768-mbit lvq family with asynchronous static ram 34 datasheet 8.0 power and reset specifications refer to the latest revision of the intel strataflash ? wireless memory system (lv18/lv30 scsp; 1024-mbit lv family datasheet (order number 253854) for details not included in this document. figure 18. psram mode register updatetiming waveform hi ghest addr ess h ighest addr ess h ighest addr ess h ighest addr ess 0000h 000xh w7 w4 w7 w4 w8 w3 w8 w3 mode register setting w1 w1 w1 w1 r1 r1 r1 r1 address p-cs# r-oe# r-we# data i/o r-ub#, r-lb#
768-mbit lvq family with asynchronous static ram datasheet 35 9.0 design guide: operation overview 9.1 bus operations with f-ce# low and f-rst# high, the flash dies are enabled for normal operations. the flash device internally decodes upper address inputs to determine the accessed partition or block. in an asynchronous read operation, addresses are latched when adv# transition from v il to v ih , or continuously flows through if adv# is held low. in synchronous-burst mode, addresses are latched by the rising edge of adv# or the next valid clk edge when adv# is low. table 13, flash + psram + sram bus operations summarizes the bus operations and voltage levels that must be applied to individual flash die in each mode note: each flash die within the 768-mbit lvq family with asynchronous static ram device shares basic asynchronous read and write operations unless otherwise specified. table 13. flash + psram + sram bus operations (sheet 1 of 2) device mode f-rst# f1-ce# f2-ce# f-oe# f-we# wait adv# f-vpp s-cs1# s-cs2 p-mode p-cs# r-oe# r-we# r-ub#, r-lb# d[15:0] notes flashdie #1 (code) synchronous array and non- array read hlhlh active l x hxx h xx x flash d out 1,2,3,4 ,5,6,9 asynchronous read h l h l h deasserted l x h xx h xx x flash d out 1,2,3,4 ,5,6,9 write h l h h l deasserted l v pp1 or v pp2 h xx h xx x flash d in 3,4,6 output disable h l h h h high-z x high-z any xsram mode allowed flash high-z 4 standby h h h x x high-z x high-z flash high-z 4 reset lxxxx high-z xhigh-z flash high-z 4 flash die #2 (data) synchronous array and non- array read h h l l h deasserted l x hxxhxx x flash die #2 d out 1,2,3,4 ,5,6,9 async read h h l l h deasserted l x hxxhxx x flash die #2 d out 1,2,3,4 ,5,6,9 write h h l h l deasserted l vpp1 or vpp2 hxxhxx x flash die #2 d out 3,4,6 output disable h h l h h high-z x high-z any xsram mode allowed flash# 2 high- z 4 standby h h h x x high-z x high-z flash #2 high-z 4 reset lxxxx high-z xhigh-z flash #2 high-z 4
768-mbit lvq family with asynchronous static ram 36 datasheet 9.2 flash device commands and command definitions refer to the intel strataflash ? wireless memory system (lv18/lv30 scsp), 1024-mbit lv family datasheet (order number 253854) for complete descriptions of flash modes and commands, for command bus-cycle definitions, and for flowcharts that illustrate operational routines. note: each flash die within the 768-mbit lvq family with asynchronous static ram device shares basic asynchronous read and write operations unless otherwise specified. psram (#1 or #2) read x h l x x high-z x x h h h l l h l psram d out 1,3 write x h l x x high-z x x h h h l h l l psram d in 3 output disable any flash or sram mode allowed hhhlhh x psram high-z 4 standby hhhhxx x psram high-z 4 low-power mode h hl xxx x psram high-z 4 sram enabled read x x x high-z x x l h x h l h l sram d out 1,3,8 write x x x high-z x x l h x h h l l sram d in 3,8 output disable any flash or psram mode allowed lhxhhh x sram high-z 3,8 standby h h x h x x x sram high-z 4,8 data retention same as sram standby sram high-z 7,8 notes: 1. wait is active during sync burst read when f-ce# and oe# are asserted. wait is high-z if f-ce# or oe# is deasserted. 2. fx-ce# is f1-ce# for flash #1, f2-ce# for flash #2, and f3-ce# for flash #3. fx-oe# is f1-oe# for flash #1, and f2- oe# for flash #2. 3. for flash, fx-oe# and f-we# should never be asserted simultaneously. for psram or sram, r-oe# and r-we# should never be asserted simultaneously. 4. x can be v il or v ih for inputs and v pp1, v pp2 ,v pplk or v pph for f-vpp. 5. flash cfi query and status register accesses use d[7:0] only, all other reads use d[15:0]. 6. refer to intel strataflash ? wireless memory system datasheet for valid d in during flash writes. 7. the sram can be placed into data retention mode by lowering s-vcc to the v dr limit when in standby mode. 8. p-mode is high if psram is in standby. p-mode is low if psram is in low-power mode. please see section 18.0, psram operations on page 45 for more details on standby and low-power mode. 9. data segment flash only operates in asynchronous mode, clk is ignored and wait is deasserted. table 13. flash + psram + sram bus operations (sheet 2 of 2) device mode f-rst# f1-ce# f2-ce# f-oe# f-we# wait adv# f-vpp s-cs1# s-cs2 p-mode p-cs# r-oe# r-we# r-ub#, r-lb# d[15:0] notes
768-mbit lvq family with asynchronous static ram datasheet 37 10.0 flash read operation refer to the latest revision of the intel strataflash ? wireless memory system (lv18/lv30 scsp; 1024-mbit lv family datasheet (order number 253854) for details not included in this document. 11.0 flash program operation refer to the latest revision of the intel strataflash ? wireless memory system (lv18/lv30 scsp; 1024-mbit lv family datasheet (order number 253854) for details not included in this document. 12.0 flash erase operation refer to the latest revision of the intel strataflash ? wireless memory system (lv18/lv30 scsp; 1024-mbit lv family datasheet (order number 253854) for details not included in this document. 13.0 flash suspend and resume operations refer to the latest revision of the intel strataflash ? wireless memory system (lv18/lv30 scsp; 1024-mbit lv family datasheet (order number 253854) for details not included in this document. 14.0 flash block locking and unlocking operations refer to the latest revision of the intel strataflash ? wireless memory system (lv18/lv30 scsp; 1024-mbit lv family datasheet (order number 253854) for details not included in this document. 15.0 flash protection register operation refer to the latest revision of the intel strataflash ? wireless memory system (lv18/lv30 scsp; 1024-mbit lv family datasheet (order number 253854) for details not included in this document. 16.0 flash configuration operation refer to the latest revision of the intel strataflash ? wireless memory system (lv18/lv30 scsp; 1024-mbit lv family datasheet (order number 253854) for details not included in this document.
768-mbit lvq family with asynchronous static ram 38 datasheet 17.0 dual operation considerations 17.1 product configurations and memory partitioning by default, the first flash die is the first code segment flash die, a fast, execute-in-place (xip) solution ideal for an instruction fetch application. this portion is the user-selected parameter configuration option, made up of either a 128-mbit flash die or a 256-mbit flash die, each containing one parameter partition and several main partitions. the parameter partition contains four 16-kword parameter blocks and seven 64-kword main blocks; all main partitions consist of eight 64-kword main blocks. the large, embedded data segment is a single partition asynchronous page-mode read device that can be made up of multiple dies with densities of 128-mbit or 256-mbit. the single partition is made up of four 16-kword parameter blocks and 64-kword main blocks. the data segment flash die parameter configuration will always be the opposite of the code segment flash die parameter configuration. see table14onpage39 for examples of configuration options. the code and embedded data portions of the lvq device are both asymmetrical in blocking. each memory block features zero-latency block locking. data integrity is protected even further with the optional use of f-vpp and f-wp# to implement block lock down. the user has the choice of selecting either a top or a bottom parameter partition configuration for the code segment flash die. depending on the choice of configuration, the data segment flash die in the lvq device will be parametrically opposed. for instance, if the user selects top parameter configuration for the code segment flash die, the data segment flash die in the package will be configured as bottom parameter configuration, and vice-versa. this ensures the largest number of contiguous main block addresses for software efficiency. the xram segment can consist of up to two pseudo-sram (psram) dies and one sram die with the following possible densities: ? the first psram die can have a density of 64-mbit or 128-mbit. ? the second psram die can have a density of 64-mbit or 32-mbit. ? the sram die has a density of 8-mbit. for the code segment, the 128-mbit flash die has an 8-mbit partition block and the 256-mbit flash die has a 16-mbit partition block. the minimum code + data density combination for the lv18/ lv30 family is 384 mbit.
768-mbit lvq family with asynchronous static ram datasheet 39 . table 14. lvq die stacked configuration example (top / bottom parameter) 17.2 product segment unique features the code segment of the 768-mbit lvq family with asynchronous static ram device includes the following enhanced features unless specifically noted otherwise: ? 64 unique (intel pre-programmed) identifier bits and 2,112 user-programmable otp bits for each code segment flash die. figure 19. top and bottom parameter configurations code (top) data (bottom) top parameter partition block stacking convention data (top) parameter blocks main blocks 1-code + 1- data 1-code + 2- data 2-code + 1- data 2-code + 2 - data code (top) code (top) code (top) code (top) code (bottom) data (bottom) data (bottom) data (bottom) data (top) data (top) code (bottom) bottom parameter partition block stacking convention parameter blocks main blocks 1-code + 1- data 1-code + 2- data 2-code + 1- data 2-code + 2 - data data (bottom) code (bottom) code (bottom) code (bottom) data (top) data (top) code (top) code (bottom) data (bottom) data (top) stacked configuration example (top parameter) die stack configuration flash die#1 (user selected) flash die #2 flash die #3 code only top na na code+data top bottom na code+data+data top top bottom code+code+data top top bottom stacked configuration example (bottom parameter) die stack configuration flash die#1 (user selected) flash die #2 flash die #3 code bottom na na code+data bottom top na code+data+data bottom bottom top code+code+data bottom bottom top
768-mbit lvq family with asynchronous static ram 40 datasheet ? traditional write, erase, and burst-mode read capabilities of intel ? wireless flash memory. ? simultaneous rww/rwe operations, enabling a burst read operation in one partition while simultaneous with program or erase operations in other partitions. ? burst-read across partition boundaries, but not across segment dies within the subsystem. note: user application code is responsible for ensuring that burst-mode reads do not cross into a partition that is in program or erase mode. the embedded data segment includes the following features unless specifically noted otherwise: ? high density offerings of up to 512 mb designated specifically for large embedded data. ? single partition asynchronous page-mode read operation, allowing for a cost-effective ideal storage format. ? read-while-program or read-while-erase operations can be accomplished with software through program suspend and erase suspend operations. 17.3 flash die memory map the 768-mbit lvq family with asynchronous static ram device is available in several density and parameter configurations. the memory map is based on the stacking of individual flash die density options of 128 mbit or 256 mbit. the memory map shows individual flash die configurations and block/partition allocations. the code segment flash die is made up of 128-mbit dies or 256-mbit dies, each containing one parameter partition and several main partitions. the 128-mbit memory array is divided into sixt een 8-mbit partitions. each die density contains one parameter partition and fifteen main partitions. the 8-mbit top or bottom parameter partition contains four 16-kword blocks and seven 64-kword blocks. each of the remaining fifteen 8-mbit main partitions contains eight 64-kword blocks. the 256-mbit memory array is divided into sixteen 16-mbit partitions. each device contains one parameter partition and fifteen main partitions. the 16-mbit top or bottom parameter partition contains four 16-kword blocks and fifteen 64-kword blocks. each of the remaining fifteen 16- mbit main partitions contains sixteen 64-kword blocks. the data segment flash die density is made up of 128-mbit dies or 256-mbit dies, each containing a single partition architecture made up of four 16-kword parameter blocks and 64-kword main blocks. the memory map and partitioning for various flash die combinations, top and bottom parameters and are shown in the following tables: note: only 128-mbit and 256-mbit flash die densities are used in three flash die scsp combinations. ? table 17, three flash dies (top parameter) scsp memory map on page 43 ? table 15, two flash dies (top parameter) scsp memory map on page 41 ? table 16, two flash dies (bottom parameter) scsp memory map on page 42 ? table 18, three flash dies (bottom parameter) scsp memory map on page 44
768-mbit lvq family with asynchronous static ram datasheet 41 table 15. two flash dies (top parameter) scsp memory map flash die# die stack configuration partitioning block size (kw) partition size (mbit) 128-mbit flash partition size (mbit) 256-mbit flash blk# address range blk# address range 1 code (top parameter) parameter partition (partition 0) 16 8 130 7fc000-7fffff 16 258 ffc000-ffffff ... ... ... ... ... 16 127 7f0000-7f3fff 255 ff0000-ff3fff 64 126 7e0000-7effff 254 fe0000-feffff ... ... ... ... ... 64 120 780000-78ffff 240 f00000-ffffff main partitions (partition1to7) 64 119 770000-77ffff 239 ef0000-efffff ... ... ... ... 64 64 400000-4fffff 128 800000-80ffff main partitions (partition 8 to 15) 64 63 3f0000-3fffff 127 f70000-f7ffff ... ... ... ... ... 64 0 000000-00ffff 0 000000-00ffff 2 data (bottom parameter) single partition 4 x 16-kword parameter blocks 127 x 64-kword main blocks (128-mb) 255 x 64-kword main blocks (256-mb 64 130 7f0000-7fffff 258 ff0000-ffffff ... ... ... ... ... 64 67 400000-40ffff 131 100000-10ffff 64 66 3f0000-3fffff 130 7f0000-7fffff ... ... ... ... ... 64 11 080000-08ffff 11 080000-08ffff 64 10 070000-07ffff 10 070000-07ffff ... ... ... ... ... 64 4 010000-01ffff 4 010000-01ffff 16 3 00c000-00ffff 3 00c000-00ffff ... ... ... ... ... 16 0 000000-003fff 0 000000-003fff
768-mbit lvq family with asynchronous static ram 42 datasheet table 16. two flash dies (bottom parameter) scsp memory map flash die# die stack configuration partitioning block size (kw) partition size (mbit) 128-mbit flash partition size (mbit) 256-mbit flash blk# address range blk# address range 1 data (top parameter) single partition 4 x 16-kword parameter blocks 127 x 64-kword main blocks (128-mb) 255 x 64-kword main blocks (256-mb 16 130 7f0000-7fffff 258 ff0000-ffffff ... ... ... ... ... 16 67 400000-40ffff 131 100000-10ffff 64 66 3f0000-3fffff 130 7f0000-7fffff ... ... ... ... ... 64 11 080000-08ffff 11 080000-08ffff 64 10 070000-07ffff 10 070000-07ffff ... ... ... ... ... 64 4 010000-01ffff 4 010000-01ffff 64 3 00c000-00ffff 3 00c000-00ffff ... ... ... ... ... 2 code (bottom parameter) parameter partition (partition 0) 64 8 130 7fc000-7fffff 16 258 ffc000-ffffff ... ... ... ... ... 64 127 7f0000-7f3fff 255 ff0000-ff3fff 64 126 7e0000-7effff 254 fe0000-feffff ... ... ... ... ... 64 120 780000-78ffff 240 f00000-ffffff main partitions (partition 1 to 7) 64 119 770000-77ffff 239 ef0000-efffff ... ... ... ... 64 64 400000-4fffff 128 800000-80ffff main partitions (partition 8 to 15) 16 63 3f0000-3fffff 127 f70000-f7ffff ... ... ... ... ... 16 0 000000-00ffff 0 000000-00ffff
768-mbit lvq family with asynchronous static ram datasheet 43 table 17. three flash dies (top parameter) scsp memory map flash die# die stack configuration partitioning block size (kw) partition size (mbit) 128-mbit flash partition size (mbit) 256-mbit flash blk# address range blk# address range 1 code (top parameter) parameter partition (partition 0) 16 8 130 7fc000-7fffff 16 258 ffc000-ffffff ... ... ... ... ... 16 127 7f0000-7f3fff 255 ff0000-ff3fff 64 126 7e0000-7effff 254 fe0000-feffff ... ... ... ... ... 64 120 780000-78ffff 240 f00000-ffffff main partitions (partition1to7) 64 119 770000-77ffff 239 ef0000-efffff ... ... ... ... 64 64 400000-4fffff 128 800000-80ffff main partitions (partition8to15) 64 63 3f0000-3fffff 127 f70000-f7ffff ... ... ... ... ... 64 0 000000-00ffff 0 000000-00ffff 2 code (top parameter) parameter partition (partition 0) 16 8 130 7fc000-7fffff 16 258 ffc000-ffffff ... ... ... ... ... 16 127 7f0000-7f3fff 255 ff0000-ff3fff 64 126 7e0000-7effff 254 fe0000-feffff ... ... ... ... ... 64 120 780000-78ffff 240 f00000-ffffff main partitions (partition1to7) 64 119 770000-77ffff 239 ef0000-efffff ... ... ... ... 64 64 400000-4fffff 128 800000-80ffff main partitions (partition8to15) 64 63 3f0000-3fffff 127 f70000-f7ffff ... ... ... ... ... 64 0 000000-00ffff 0 000000-00ffff 3 data (bottom parameter) single partition 4 x 16-kword parameter blocks 127 x 64-kword main blocks (128-mb) 255 x 64-kword main blocks (256-mb) 64 130 7f0000-7fffff 258 ff0000-ffffff ... ... ... ... ... 64 67 400000-40ffff 131 100000-10ffff 64 66 3f0000-3fffff 130 7f0000-7fffff ... ... ... ... ... 64 11 080000-08ffff 11 080000-08ffff 64 10 070000-07ffff 10 070000-07ffff ... ... ... ... ... 64 4 010000-01ffff 4 010000-01ffff 16 3 00c000-00ffff 3 00c000-00ffff ... ... ... ... ... 16 0 000000-003fff 0 000000-003fff
768-mbit lvq family with asynchronous static ram 44 datasheet table 18. three flash dies (bottom parameter) scsp memory map flash die# die stack configuration partitioning block size (kw) partition size (mbit) 128-mbit flash partition size (mbit) 256-mbit flash blk# address range blk# address range 1 data (top parameter) single partition 4 x 16-kword parameter blocks 127 x 64-kword main blocks (128-mb) 255 x 64-kword main blocks (256-mb) 16 130 7f0000-7fffff 258 ff0000-ffffff ... ... ... ... ... 16 67 400000-40ffff 131 100000-10ffff 64 66 3f0000-3fffff 130 7f0000-7fffff ... ... ... ... ... 64 11 080000-08ffff 11 080000-08ffff 64 10 070000-07ffff 10 070000-07ffff ... ... ... ... ... 64 4 010000-01ffff 4 010000-01ffff 64 3 00c000-00ffff 3 00c000-00ffff ... ... ... ... ... 64 0 000000-003fff 0 000000-003fff 2 code (bottom parameter) parameter partition (partition 0) 64 8 130 7fc000-7fffff 16 258 ffc000-ffffff ... ... ... ... ... 64 127 7f0000-7f3fff 255 ff0000-ff3fff 64 126 7e0000-7effff 254 fe0000-feffff ... ... ... ... ... 64 120 780000-78ffff 240 f00000-ffffff main partitions (partition1to7) 64 119 770000-77ffff 239 ef0000-efffff ... ... ... ... 64 64 400000-4fffff 128 800000-80ffff main partitions (partition 8 to 15) 16 63 3f0000-3fffff 127 f70000-f7ffff ... ... ... ... ... 16 0 000000-00ffff 0 000000-00ffff 3 code (bottom parameter) parameter partition (partition 0) 64 8 130 7fc000-7fffff 16 258 ffc000-ffffff ... ... ... ... ... 64 127 7f0000-7f3fff 255 ff0000-ff3fff 64 126 7e0000-7effff 254 fe0000-feffff ... ... ... ... ... 64 120 780000-78ffff 240 f00000-ffffff main partitions (partition1to7) 64 119 770000-77ffff 239 ef0000-efffff ... ... ... ... 64 64 400000-4fffff 128 800000-80ffff main partitions (partition 8 to 15) 16 63 3f0000-3fffff 127 f70000-f7ffff ... ... ... ... ... 16 0 000000-00ffff 0 000000-00ffff
768-mbit lvq family with asynchronous static ram datasheet 45 18.0 psram operations 18.1 psram power-up sequence and initialization the psram functionality and reliability are independent of the power-up slew rate of the core p- v cc . any power-up slew rate is possible under use conditions. the following power-up sequence and operation should be used before starting normal operation. the psram power-up sequence is represented in figure 20 . at power-up, hold p-mode low for the period of t vhmh and transition p-cs# from low to high before transitioning p-mode to a logical high. p-cs# and p-mode must be held high for the period of t mhcl before normal psram operation is possible once the power up sequence is complete. 18.2 psram mode register the psram die has an internal register that helps control the low-power mode of the psram. this register is called the mode register. a fraction of the psram array can be enabled for refresh by setting the mode register. available fixed, partial-refresh fraction densities are 16 mbit, 8 mbit, 4 mbit and 0 mbit for all density options. once the refresh density has been set in the mode register, these settings are retained until they are set again while applying the power supply. however, the mode register setting will become undefined if the power is turned off; therefore, it is important that the mode register is set again after power application. figure 20. timing waveform for psram power-up sequence table 19. psram initialization timing parameter symbol min max unit power application to p-mode low-level hold t vhmh 50 C s p-cs# high-level to p-mode high-level t chmh 0Cns following power application, p-mode high- levelholdtop-cs#low-level t mhcl 200 C s tvhmh tmhcl tchmh initialization vcc (min) normal operation p-cs# p-mode p-vcc
768-mbit lvq family with asynchronous static ram 46 datasheet 18.2.1 psram mode register setting since the initial value of the psram mode register at power application is undefined, the mode register must be set after initialization at power application. when setting the density of partial refresh, data is not guaranteed before entering the low-power mode. (this is the same for reset.) however, since low-power mode is not entered unless p-mode is a logical low, when partial refresh is not used, it is not necessary to set the mode register. also, when using page read without using partial refresh, it is not necessary to set the mode register. the psram mode register setting can be entered by successively writing two specific data after two continuous reads of the highest address. the mode register setting is a continuous four-cycle operation: two read cycles and two writes cycles. see table 20 for setting psram mode register command sequence. figure 21, psram mode register setting flowchart on page 47 shows the steps in setting the mode register. figure 18 on page 34 illustrates the timing waveform. table 20. setting psram mode register command sequence command sequence 1st bus cycle (read cycle) 2nd bus cycle (read cycle) 3rd bus cycle (write cycle) 4th bus cycle (write cycle) partial refresh density address data address data address data address data 16-mbit highest address _ highest address _ highest address 0x00 highest address 0x04 8-mbit highest address _ highest address _ highest address 0x00 highest address 0x05 4-mbit highest address _ highest address _ highest address 0x00 highest address 0x06 0-mbit highest address _ highest address _ highest address 0x00 highest address 0x07
768-mbit lvq family with asynchronous static ram datasheet 47 note: xxh=0x04, 0x05, 0x06 or 0x07 18.2.2 cautions for setting psram mode register for the psram mode register setting, the internal counter status is judged by toggling p-cs# and r-oe#. therefore, toggle p-cs# at every cycle during entry (read cycle twice, write cycle twice), and toggle r-oe# like p-cs# at the first and second read cycles. if incorrect addresses or data are written, or are written in an incorrect order, the setting of the psram mode register will be set incorrectly. when the highest address is read consecutively three or more times, the mode register setting entries are not performed correctly. note: immediately after the highest address is read, the setting of the mode register is not performed correctly. perform the setting of the mode register after power application or after accessing other than the highest address. once the refresh density has been set in the mode register, the setting is retained until it is reset again while power is continuously applied. however, the mode register setting becomes undefined if the power is turned off. the mode register must be reset after after any power cycle. figure 21. psram mode register setting flowchart data=00h write to highest address data=xxh begin normal operation read highest address by toggling both p-cs# and r-oe# start write to highest address read highest address by toggling both p-cs# and r-oe# fail mode register setting exit no no no no no no
768-mbit lvq family with asynchronous static ram 48 datasheet 18.3 psram low-power mode in addition to the regular standby mode with a full density data hold, low-power mode performs partial density data refresh or zero density data refresh. the low-power mode allows the user to turn off sections of the psram die to save refresh current. the psram die is divided into four sections allowing certain sections to be refreshed with p-mode at a logical-low. in regular standby mode, both p-cs# and p-mode are logical-high. but in low-power mode, p- mode is a logical-low. in low-power mode, if 0-mbit setting is set as the density, it is necessary to perform initialization the same way as after applying power in order to return to normal operation from low-power mode. refer to figure 20, timing waveform for psram power-up sequence on page 45 for timing charts. when the density has been to set to 16 mbit, 8 mbit, or 4 mbit in low-power mode, it is not necessary to perform initialization to return to normal operation from low-power mode. refer to figure 22, psram low-power mode entry/exit (16-, 8-, 4-, 0-mbit) waveform for timing charts. figure 22. psram low-power mode entry/exit (16-, 8-, 4-, 0-mbit) waveform tmhcl1/tmhcl2 tchml low power mode (partial array refresh/zero refresh) p-mode p-cs# table 21. psram low-power mode entry/exit timing parameter description min max unit t chml low-power mode entry, p-cs# high-level to p-mode# low-level 0 C ns t mhcl1 1 low-power mode (16-, 8-, 4-mbit hold) exit to normal operation, p-mode high-level to p-cs# low-level 30 C ns t mhcl2 2 low-power mode (0-mbit data hold) exit to normal operation, p-mode high-level to p-cs# low-level 200 C s notes: 1. t mhcl1 is the time it takes to return to normal operation from low-power mode (data hold: 16-, 8-, 4-mbit). 2. t mhcl2 is the time it takes to return to normal operation from low-power mode (0-mbit data hold).
768-mbit lvq family with asynchronous static ram datasheet 49 appendix a write state machine refer to the latest revision of the intel strataflash ? wireless memory system (lv18/lv30 scsp; 1024-mbit lv family datasheet (order number 253854) for details not included in this document. appendix b common flash interface refer to the latest revision of the intel strataflash ? wireless memory system (lv18/lv30 scsp; 1024-mbit lv family datasheet (order number 253854) for details not included in this document. appendix c flash flowcharts refer to the latest revision of the intel strataflash ? wireless memory system (lv18/lv30 scsp; 1024-mbit lv family datasheet (order number 253854) for details not included in this document.
768-mbit lvq family with asynchronous static ram 50 datasheet appendix d additional information : order number document 253853 intel strataflash ? wireless memory system (lv 18/30 scsp); 1024-mbit lvx family datasheet 253854 intel strataflash ? wireless memory system (lv 18/30 scsp); 1024-mbit lv family datasheet notes: 1. please call the intel literature center at (800) 548-4725 to request intel documentation. international customers should contact their local intel or distribution sales office. 2. for the most current information on intel ? flash memory products, software and tools, visit our website at http://developer.intel.com/design/flash.
768-mbit lvq family with asynchronous static ram datasheet 51 appendix e ordering information figure 23 shows the decoder for the flash-only combinations in the 768-mbit lvq family with asynchronous static ram device. figure 24 shows the decoder for the flash + ram combinations in the 768-mbit lvq family with asynchronous static ram device. figure 23. decoder for flash-only combinations f 0 0 l v y d q 8 z 4 n package pinout indicator flash density voltage product family 0=nodie 2 = 64-mbit 3 = 128-mbit 4 = 256-mbit y = 1.8 volt core and i/o z= 3volti/o,1.8voltcore q= quad+ ballout 0 0 0 parameter location device details flash #1 flash #3 flash #4 flash #2 flash family 1/2 flash family 3/4 product line designator 48f = flash memory only scsp packages: ! rd = scsp ! nz = intel ? ultra-thin scsp lead-free scsp packages: ! pf = scsp ! jz = intel ? ultra-thin scsp b = bottom parameter t = top parameter d = bottom parameter for flash die #1, top parameter for flash die #2 l = intel strataflash ? wireless flash memory (l18/l30) v = intel strataflash ? wireless flash memory system (lv18/lv30) 0 = no die 1 = original version of the products i.e. for this specific example: speed (code die): ! 90 ns aysnc/14 ns sync for 256m flash @ 1.7 v - 2.0 v i/o ! 85 ns aysnc/14 ns sync for 256m flash @ 1.8 v - 2.0 v i/o speed (data die): 170 ns async @ 1.8v-2.0 v i/o 55 ns t apa async only flash process technology: 0.13 m etox? viii process
768-mbit lvq family with asynchronous static ram 52 datasheet figure 24. decoder for flash + psram combinations flash family 1 b = bottom parameter t = top parameter d = bottom parameter for flash die #1, top parameter for flash die #2 f 4 4 l v y b q 8 d 3 r package pinout indicator flash density scsp packages: ! rd = scsp ! nz = intel ? ultra-thin scsp 0=nodie 3 = 128-mbit 4 = 256-mbit q= quad+ ballout 5 0 0 parameter location product line designator 38f = flash + xram combination product family l = intel strataflash ? wireless flash memory (l18/l30) lv = intel strataflash ? wireless flash memory system (lv18/lv30) 0=nodie ram density 0=nodie 2=8-mbitram 4 = 32-mbit ram 5 = 64-mbit ram voltage y = 1.8 volt core and i/o z = 3 volt i/o, 1.8 volt core device details 1 = original version of the products i.e. for this specific example: speed (code die): ! 90 ns aysnc/14 ns sync for 256m flash @ 1.7 v - 2.0 v i/o ! 85 ns aysnc/14 ns sync for 256m flash @ 1.8 v - 2.0 v i/o speed (data die): 170nsasync@1.8v-2.0vi/o 55 ns t apa async only flash process technology: 0.13 m etox? viii process package size: 8x11x1.2mm notes: ! f1-oe# is internally shared between flas die #1 and flash die #2. f2-oe# ball is unused and should be treated as an rf u flash #1 flash #2 ram #1 ram #2 flash family 2 lead-free scsp packages: ! pf = scsp ! jz = intel ? ultra-thin scsp
768-mbit lvq family with asynchronous static ram datasheet 53 table 22. valid combinations i/o voltage combinations with 128-mbit flash combinations with 256-mbit flash 1.8 v i/o rd48f3000l0ytq0 nz48f4000l0ytq0 rd48f3000l0ybq0 nz48f4000l0ybq0 rd38f3040l0ytq0 pf48f4000l0ytq0* RD38F3040L0YBQ0 pf48f4000l0ybq0* rd48f4400l0ydq0 pf48f4400l0ydq0* rd38f4455lvytq0 rd38f4455lvybq0 3.0 v i/o rd48f3000l0ztq0 nz48f4000l0ztq0 rd48f3000l0zbq0 nz48f4000l0zbq0 rd38f3040l0ztq0 rd48f4400l0zdq0 rd38f3040l0zbq0 rd38f4050l0zbq0 rd38f3352llzdq0* rd38f4050l0ztq0 pf38f3352llzdq0* note: * these are non-standard product line items and may not be productized.
768-mbit lvq family with asynchronous static ram 54 datasheet

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